VyperCore's modified RISC-V processor will incorporate our novel hardware memory allocation management technology. This fundamental remodelling of hardware memory interfaces enables us to accelerate modern managed-language software, such as Python and C#, by up to a factor of 10. We can even achieve a >1.5x speedup on software written in older languages like C and C++.
Initially we are focusing on application software (as opposed to low-level system software) where we can maintain source code compatibility across languages (from Python to C/C++.) This will enable deployment of our accelerator card in data centers without developers needing to change their programs. Tweaked versions of popular open-source compilers and runtimes will be made available for early customers to retarget their applications. This is made much easier for us as the RISC-V community is already well underway porting tools to the architecture.
Our memory management technology is capable of eliminating the most prominent memory safety issues (such as buffer overflows and use-after-free.) Memory safety issues make up around 70% of all technical security vulnerabilities from the last 20 years (according to reports by Microsoft, Google, Apple and others.) A recent analysis by Google highlighted that not only are memory safety issues prevalent, they also make up the majority of critical and high severity problems. Our technology can make a substantial difference to secure existing and new software, without having to rewrite all the world's existing software and with a performance increase!
While the move to languages such as Rust helps to achieve compile-time safety, and is clearly a significant improvement, there remains a weakness at runtime which only hardware can resolve. Modern processor architectures fail to offer a suitable memory and security model for today's software. Our architecture takes a significant step forward in this direction, without sacrificing performance, silicon area or power.
RISC-V continues to gain momentum and offers a strong platform for us to build upon. We will be developing a clean-sheet RISC-V core and memory architecture, modifying core instructions only where necessary, and offering our managed memory extension alongside.