Accelerating & protecting compute-intensive applications

VyperCore is a fabless RISC-V processor startup
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Up to
10x
application speed-up
Memory vulnerabilities
100%
eliminated
Code changes required
Zero
Hassle-free acceleration
Ground breaking
10 years
research & development

Accelerating modern software applications

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Applicable to all general-purpose programming languages, including C/C++

VyperCore's modified RISC-V processor will incorporate our novel hardware memory allocation management technology. This fundamental remodelling of hardware memory interfaces enables us to accelerate modern managed-language software, such as Python and C#, by up to a factor of 10. We can even achieve a >1.5x speedup on software written in older languages like C and C++.

Initially we are focusing on application software (as opposed to low-level system software) where we can maintain source code compatibility across languages (from Python to C/C++.) This will enable deployment of our accelerator card in data centers without developers needing to change their programs. Tweaked versions of popular open-source compilers and runtimes will be made available for early customers to retarget their applications. This is made much easier for us as the RISC-V community is already well underway porting tools to the architecture.

Enforced memory safety

Our memory management technology is capable of eliminating the most prominent memory safety issues (such as buffer overflows and use-after-free.) Memory safety issues make up around 70% of all technical security vulnerabilities from the last 20 years (according to reports by Microsoft, Google, Apple and others.) A recent analysis by Google highlighted that not only are memory safety issues prevalent, they also make up the majority of critical and high severity problems. Our technology can make a substantial difference to secure existing and new software, without having to rewrite all the world's existing software and with a performance increase!

While the move to languages such as Rust helps to achieve compile-time safety, and is clearly a significant improvement, there remains a weakness at runtime which only hardware can resolve. Modern processor architectures fail to offer a suitable memory and security model for today's software. Our architecture takes a significant step forward in this direction, without sacrificing performance, silicon area or power.

Extended RISC-V processor architecture

RISC-V continues to gain momentum and offers a strong platform for us to build upon. We will be developing a clean-sheet RISC-V core and memory architecture, modifying core instructions only where necessary, and offering our managed memory extension alongside.

RISC-V logo

Our team

VyperCore is a brand new startup, looking for motivated and capable engineers to join us!

We're looking for people to join and lead our technical development. Our founding team brings strong commercial and technical leadership.

Russell Haggar

Russell Haggar

CEO & Chair, Co-founder

Recovered venture capital investor, seasoned tech leader, semiconductor adviser, and serial hardtech starter-upper.

Picture of Ed Nutting (CTO of VyperCore)

Ed Nutting

CTO, Co-founder

Originator of VyperCore's technology and experienced in formal proof, software development and technical leadership.

You?

Engineer

We're looking for hardware and software engineers based in Cambridge and Bristol, with hybrid working patterns if desired.

Interested in joining us?