"VyperCore shows RTL simulation of RISC-V core, plans hardware"

EE News reports on VyperCore's major development milestone, running the first version of its new 64-bit RISC-V processor in simulation, executing live Python code on its hardware-based garbage collector technology, demonstrating the ability to totally sidestep the performance-damaging garbage collection software algorithms buried within the Python Runtime.

Read the article here: https://www.eenewseurope.com/en/vypercore-shows-rtl-simulation-of-risc-v-core-plans-hardware